1. Field of the Invention
The present invention relates to a magnetic reproducing apparatus such as a floppy disk drive or hard disk drive.
2. Description of the Prior Art
A conventional magnetic reproducing apparatus will be described. FIG. 3 is a circuit diagram of a reading circuit 40 in a conventional magnetic reproducing apparatus. In FIG. 3, a magnetic head 2 reads data recorded on a magnetic disk such as a floppy disk or hard disk. The two ends of the magnetic head are connected to terminals 22 and 23 of the reading circuit 40, so that the signal reproduced by the magnetic head 2 is fed to the reading circuit 40. The terminals 22 and 23 are connected to a preamplifier 24 and to an input bias setting circuit 34, respectively. The preamplifier 24 amplifies, on a differential basis, the reproduced signal fed to the terminals 22 and 23.
The preamplifier 24 outputs two amplified reproduced signals, of which one is fed to the base of an npn-type transistor Q1 and of which the other is fed to the base of an npn-type transistor Q2. The collector of the transistor Q1 is connected through a resistor R1 to a supplied voltage Vcc, and the collector of the transistor Q2 is connected through a resistor R2 to the supplied voltage Vcc.
Between the emitters of the transistors Q1 and Q2, a resistor R3 is connected. In addition, in parallel with the resistor R3, a circuit having a resistor R4 and a switch SW1 connected in series is connected. Switching of the switch SW1 is controlled by a control signal fed in via a terminal 43. Between the emitter of the transistor Q1 and ground, a constant current source circuit 25 is connected. Between the emitter of the transistor Q2 and ground, a constant current source circuit 26 is connected. The transistors Q1 and Q2, the resistors R1, R2, and R3, the serial circuit composed of the resistor R4 and the switch SW1, and the constant current source circuits 25 and 26 together constitute a differential amplifier circuit 38.
The collector of the transistor Q1 is connected to the base of an npn-type transistor Q3. The collector of the transistor Q2 is connected to the base of an npn-type transistor Q4. The collector of the transistor Q3 is connected to the supplied voltage Vcc. The collector of the transistor Q4 is connected to the supplied voltage Vcc. Between the emitter of the transistor Q3 and ground, a constant current source circuit 27 is connected. Between the emitter of the transistor Q4 and ground, a constant current source circuit 28 is connected. The emitter of the transistor Q3 is connected to an output terminal 35. The emitter of the transistor Q4 is connected to an output terminal 36.
The amplified reproduced signal output from the preamplifier 24 are further amplified on a differential basis by a differential amplifier circuit 41 that produces a single output. The output of this differential amplifier circuit 41 is fed to one input terminal of a comparator 42. To the other input terminal of the comparator 42, a reference voltage Va is fed. The comparator 42 compares the output of the differential amplifier circuit 41 with the reference voltage Va, and feeds the comparison result to the input bias setting circuit 34. The differential amplifier circuit 41, the comparator 42, and the input bias setting circuit 34 together constitute a thermal asperity circuit 50.
This conventional magnetic reproducing apparatus operates in the following manner. The signal reproduced by the magnetic head 2 is first amplified by the preamplifier 24 and is then fed to the differential amplifier circuit 38. The amplification factor of the differential amplifier circuit 38 depends on the state of the switch SW1. Specifically, when the switch SW1 is on, the resistors R3 and R4 are kept connected in parallel, and thus offer a smaller composite resistance. This reduces the resistance present on the emitter side of the transistors Q1 and Q2, and thus increases the amplification factor of the differential amplifier circuit 38. By contrast, when the switch SW1 is off, the resistor R4 is disconnected from the rest of the circuitry. This increases the resistance present on the emitter side of the transistors Q1 and Q2, and thus reduces the amplification factor of the differential amplifier circuit 38. Note that switching of the switch SW1 is performed in accordance with the resistance of the magnetic head 2 and the level of the read signal.
Thus, the amplification factor of the differential amplifier circuit 38 is switched by the control signal fed in via the terminal 43. The amplified reproduced signals are extracted from the collectors of the transistors Q1 and Q2, and are then fed through the transistors Q3 and Q4, provided as a final stage, to the output terminals 35 and 36 respectively for output.
In a case where the magnetic head 2 is, for example, a magnetic head provided with a magnetic resistance device (hereafter referred to as an "MR head"), the MR head 2 exhibits a higher equivalent resistance as it generates heat from contact with the magnetic disk. As the resistance of the MR head 2 increases, the bias voltage produced across that resistance by the current i output from the input bias setting circuit 34 increases accordingly.
The thermal asperity circuit (compensation circuit) 50, by monitoring this bias voltage, compensates for variation in the bias voltage so as to keep it stably at a constant voltage. In the thermal asperity circuit 50, the signal output from the preamplifier 24 is amplified by the differential amplifier circuit 41, and the resulting output is compared with the reference voltage Va by the comparator 42. The comparator 42 feeds the comparison result, either a high level or a low level, to the input bias setting circuit 34. The input bias setting circuit 34 is controlled by the output of the comparator 42 in such a way as to reduce the current i it feeds to the magnetic head 2 and thereby reduce the bias voltage across the magnetic head 2 when the bias voltage becomes higher than the reference voltage specified by the reference voltage Va.
In the differential amplifier circuit 38, the base bias of the transistor Q1 is as indicated by B1 in FIG. 4A, and the base bias of the transistor Q2 is as indicated by B2 in FIG. 4A. An increase in the bias voltage resulting from an increase in the resistance of the magnetic head 2 causes an increase in the voltage difference W (bias) between those base biases B1 and B2 as a result of, for example, B2 shifting upward and B1 shifting downward (B2 may remain fixed). However, the above-described thermal asperity circuit 50 acts to keep the bias constant, and therefore the base biases B1 and B2 can safely be regarded as kept substantially fixed.
However, this conventional magnetic reproducing apparatus tends to suffer from distortion that appears in the output signal when the switch SW1 is turned on to increase the amplification factor of the differential amplifier circuit 38. Specifically, whereas no problem arises as long as the reproduced signals S1 and S2 remain relatively small throughout as shown in FIG. 4A, when the signals S1 and S2 have large portions, they may go out of the dynamic range into the saturation region as shown in FIG. 4B when the amplification factor of the differential amplifier circuit 38 is increased. This causes distortion in the output signal.